The present application claims priority under 35 U.S.C. xc2xa7119 to Japanese Application No. 2000-117989 filed on Apr. 19, 2000, which is hereby incorporated by reference its entirely for all purposes.
1. Field of The Invention
The present invention relates to a data generation circuit which can store and read picture processing data and to a method for generating data. In particular, the present invention relates to an orthogonal transforming circuit and method.
2. Description of the Related Art
Compressing and extracting techniques are generally performed in the processing of moving picture data. Original moving picture data is compressed into a variable-length code using a coding circuit. The original moving picture data is extracted from the coded data by a decoding circuit.
The coding circuit includes a Discrete Cosine Transformation (DCT) circuit, a quantizing circuit and a variable-length coding circuit. The decoding circuit includes an Inverse Discrete Cosine Transformation (IDCT) circuit, an inverse-quantizing circuit and a variable-length code decoding circuit.
The DCT circuit and the IDCT circuit are generally called an orthogonal transforming circuit. In the orthogonal transforming circuit, for example, DCT coefficients are inverse-quantized, and inputted to the IDCT circuit as data. The data generation circuit is applied to generate data, which are inputted to such an orthogonal transforming circuit.
The data generation circuit has a memory to store and read picture processing data, such as inverse-quantized DCT coefficients data. A serial port Random Access Memory (RAM) and a dual port RAM are conventionally used as such a memory.
A unit block of the moving picture data for data processing is 8*8 pixels or 16*16 pixels, in accordance with the international standard MPEG2 (Moving Picture Image Coding Experts Group Phase 2). Therefore, the memory is divided into a plurality of storing areas. Each storing area corresponds to each pixel. Each inverse-quantized DCT coefficient corresponding to each pixel is stored in the respective storing areas. For example, a 64 word RAM is used for unit block of 8*8 pixels since each pixel must be accessible separately according to address information.
Most of the picture processing data, such as inverse-quantized DCT coefficients, which are stored in the memory of the data generation circuit, are zero-components (data equivalent to data xe2x80x9cBxe2x80x9d). Even though the rate of zero-components in one unit block depends on the coding method and the picture that is coded or decoded, there are still a lot of zero-components. In a conventional data generating circuit, all of the zero components are stored to the storing areas in order of scanning, and all of the zero-components are read out after the transformation in the orthogonal direction.
Power consumption is large in the conventional data generating circuit because all of the data including zero-components are written into the memory. Also, a writing period is long because the entire picture processing data is written into the memory. Therefore, the processing time is slow.
An example of an attempt to solve this problem is disclosed in the application of Japanese laid open number HEI 8-167856. In this reference, a RAM is initialized before writing, and then the data except for the zero-components are written. In addition, the data generating circuit of this reference includes a plurality of RAMs. While the picture processing data of one RAM are read out, another RAM is initialized and written to improve the processing time.
However, in the circuit of this reference, a plurality of RAMs have to be prepared and more complicated operation is required which increases manufacturing cost. If the reference technology is performed with one RAM, which would not avoid the long processing time, complex timing control is needed because the RAM has to be initialized before writing
According to one aspect of the present invention, a data generating circuit includes a memory which writes picture data into a plurality of storage areas and reads the picture data from the plurality of storage areas according to address information, a register which hold information indicative whether the picture data has been written into each of the plurality of storage areas, a control circuit which outputs a select signal according to the storage information held by the register when the picture data is read from the memory and a selector which selects an output data read from the memory or a fixed data according to the select signal output by the control circuit.